1. Field of the Invention
The present invention relates to an exposure apparatus that exposes each shot according to a shot arrangement on a substrate, and a device manufacturing method using the exposure apparatus.
2. Description of the Related Art
Projection exposure apparatuses used for manufacturing semiconductor devices have been required to project a circuit pattern on a reticle onto a wafer with higher resolving power along with increased fineness and density of circuits. Since the projection resolving power of a circuit pattern depends on the numerical aperture (NA) of a projection optical system and the wavelength of exposure light, high resolution can be achieved by increasing the NA of a projection optical system and using exposure light having a shorter wavelength. Regarding the latter, exposure light sources have shifted from g-line to i-line and from i-line to excimer laser. Exposure apparatuses that use excimer lasers having oscillation wavelengths of 248 nm and 193 nm have already been put to practical use. Currently, an EUV exposure technique that uses exposure light having a wavelength of 13 nm is being studied as a candidate for next-generation exposure technique.
The process for manufacturing semiconductor devices have become diversified, and techniques such as CMP (Chemical Mechanical Polishing) process have attracted attention as planarization techniques for solving the problem of insufficient focal depth in exposure apparatuses. There are great variety of structures and materials of semiconductor devices. For example, a P-HEMT (Pseudomorphic High Electron Mobility Transistor) and an M-HEMT (Metamorphe-HEMT) that are made by combining compounds such as GaAs and InP, and an HBT (Heterojunction Bipolar Transistor) that uses SiGe, SiGeC, or the like, have been proposed.
Meanwhile, increased fineness of circuit patterns has required highly precise alignment between a reticle on which a circuit pattern is formed and a wafer onto which the circuit pattern is projected. The required precision is ⅓ of the circuit line width. For example, the required precision in the current 90 nm design is 30 nm.
However, when wafer alignment is performed, a WIS (wafer induced shift) caused by the manufacturing process can occur. This WIS reduces the performance of semiconductor devices and the yield of manufacturing of semiconductor devices. The WIS is an error in the measurement of alignment marks on a wafer, caused by the device manufacturing process. The WIS is caused, for example, by the asymmetry in the structure of alignment marks or the asymmetry in the shape of photoresist applied to a wafer due to a planarization process such as a CMP process. In addition, since semiconductor devices are made through a plurality of processes, optical conditions of alignment marks differ from process to process, and variation in WIS becomes a problem.
To cope with this, in a hitherto known wafer alignment technique, the most suitable alignment parameter is selected from a plurality of alignment parameters for each process. However, to determine the most suitable alignment parameter, it is necessary to actually expose a wafer and perform overlay inspection using some parameters. This takes a lot of time. In view of such a problem, Japanese Patent Laid-Open No. 2003-203846 proposes a method for performing high precision alignment from which a WIS is removed, without optimizing the alignment parameter. In this method, a WIS is removed from the alignment result using “a quantified value of the asymmetry or the contrast of an alignment mark signal (hereinafter referred to as feature value).
In the method of Japanese Patent Laid-Open No. 2003-203846, a plurality of feature values are separately used as correction values. However, since the WIS in question on the device manufacturing scene complexly changes due to an interaction between feature values, the technique in which feature values are separately used as correction values cannot highly precisely correct the WIS. In addition, a coefficient for transforming a feature value into a correction value changes in a new device manufacturing process or when conditions of a device manufacturing process are significantly changed.